(Poistunut julkaisusta)

Trainee / Thesis worker, SoC/IP

Alkuperäinen julkaisupäivä 23.2.2021


We are looking for Trainees to SoC organization.

You would be participating in System-on-Chip system design, specification and FPGA implementation.

This work contains following aspects:

- Preparation and review of functional and design specification for SoC/IP

- RTL or HLS based FPGA design

- Designing SoC functionality from top-level down to a block level, including low level SW

- Verification and simulation of needed functionality on the block level

- Ensuring effective testing and high quality product delivery by advanced SoC verification planning, validation and testing on board

- Supporting HW/SW Bring-up and debug

- Co-operation with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues for quality


If you are familiar with some of these areas, you can be the candidate we are looking for:

- VHDL/Verilog/HLS knowhow for FPGA design

- Knowledge of SoC (ASIC/FPGA/low level SW) design and verification tools

- System modeling using Matlab

- Good knowledge of embedded systems

- Advanced verification methodologies, e.g. VMM, OVM, UVM

- LTE and 5G cellular networks and relevant Layer-1 algorithms


You are also fluent in spoken and written English. You have high motivation to learn new and work in international teams. You are a good team player.